A data network switch permits data communication among a plurality of media stations in a local area network. Data frames, or packets, are transferred between stations by means of data network switch media access control (MAC). The network switch passes data frames received from a transmitting station to a destination station based on the header information in the received data frame.
Packet transmission events typically are tracked to provide a basis for statistical analysis of network operation with respect to each data network switch port. For example, the number of transmitted packets, received packets, transmission collisions and the like can be counted and polled periodically. These significant parameters, termed objects, may be collected for purposes of statistical analysis. Through the use of statistical counters, determination can be made of improper device operation such as, for example, loss of packets.
Typically, each MAC unit may include a receive state machine and a transmit state machine having internal counters of limited capacity for counting a small number of transmission event parameters for each frame that traverses the respective switch port. Flip-flops, dedicated to the particular parameter objects, are respectively incremented each time an item in that fiame is identified. For each incoming frame, which may be temporarily stored in a receive FIFO buffer, the respective flip-flops in the receive state machine are read and the resulting data appended to the frame. For outgoing frames, similar processing takes place. This data was traditionally stored on the chip in history or status registers.
As data networks become more robust and data traffic increases, additional operational parameters become significant. The need to track all significant parameters imposes difficulties relating to increased MAC complexity. Such complexity involves the provision of more registers and supporting logic elements, as well as a requirement for larger buffer capacities. Integration of these additional elements for each MAC on the switch logic chip places a burden on chip architecture. These projected difficulties, and the relatively limited reporting functionality for the prior art arrangement, are significant disadvantages. These disadvantages are magnified if the data representing the operational parameters are retained in uncompressed format.
Some more recent network switch versions provide a RAM based memory on the switch logic chip as a full counter for data received from all of the MACs on the chip. Incorporation of a large capacity RAM in the chip to accommodate operational parameter data from all ports incurs undesirable expense. As the number of parameters increases to keep up with expanding statistical requirements, available RAM capacity must meet these needs. Polling of the RAM for external statistical diagnostic functions would require transfer of significantly increased quantities of data. Space constraints inherent in the integration of the various elements on a single logic chip impose additional drawbacks.